Answer:
BR = -16
QR = +12
(16)10 = (10000)2
(-16)10 = (01110)2
BR = 1110
(12)10 = (1100)2
QR = 1110
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Tuesday, June 21, 2011
Show step by step multiplication of the values –16 with +12 after converting them to binary, using Booths algorithm. Indicate details of sizes of the
Show step by step multiplication of the values –16 with +12 after converting them to binary, using Booths algorithm. Indicate details of sizes of the registers used.
Answer:
BR = -16
QR = +12
(16)10 = (10000)2
(-16)10 = (01110)2
BR = 1110
(12)10 = (1100)2
QR = 1110
Uploaded with ImageShack.us
Answer:
BR = -16
QR = +12
(16)10 = (10000)2
(-16)10 = (01110)2
BR = 1110
(12)10 = (1100)2
QR = 1110
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What is the need of input/output processor? How does on I/o processor support the Input-output? Compare and contrast I/o processor to Direct Memory Ac
What is the need of input/output processor? How does on I/o processor support the Input-output? Compare and contrast I/o processor to Direct Memory Access (DMA).
Ans. Need of Input/Output Processor:
1) Increased Efficiency - CPU need not wait for I/o operations to complete.
2) Direct control of CPU on I/o device.
3) Direct access of I/o module to the memory.
4) CPU is separated from the details of external I/o interfaces.
5) Use of programmed I/o - In a programmed I/o method, the responsibility of CPU is to constantly check the status of the I/o device to check whether it has become free in case output is desired, or its has finished inputting the current series of data in case input is going on.
For the above reasons, we need the I/o processor.
The I/O processor can execute specialized I/o program residing in the memory without intervention of the CPU. CPU only needs to specify a sequence of I/o activity to I/o processor. Then, I/o processor executes the necessary I/o instructions which are required for the task, and interrupts the CPU only after the entire sequence of I/o activity as specified by CPU have been completed. An advanced I/o activity as specified by CPU has been completed. An advanced I/o processor can have its own memory. An I/o processor has the additional ability to execute I/o instructions, which provide it’s a complete control of I/O operations. The architecture of I/O processor is shown below.
For high-speed devices a selector channel is used. This channel can transfer data from one high-speed device at a time. I/o modules can handle each of these high-speed devices. Therefore, I/o processors have taking the place of CPU in controlling various I/o modules.
The communication between I/o processor and CPU can be achieved by writing messages in the memory area shared by both the processors. CPU instructs I/o processor to execute an I/o program in the memory. Then the program will specify the device or devices and the area of the memory where the I/o data is stored, or to be stored.
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Ans. Need of Input/Output Processor:
1) Increased Efficiency - CPU need not wait for I/o operations to complete.
2) Direct control of CPU on I/o device.
3) Direct access of I/o module to the memory.
4) CPU is separated from the details of external I/o interfaces.
5) Use of programmed I/o - In a programmed I/o method, the responsibility of CPU is to constantly check the status of the I/o device to check whether it has become free in case output is desired, or its has finished inputting the current series of data in case input is going on.
For the above reasons, we need the I/o processor.
The I/O processor can execute specialized I/o program residing in the memory without intervention of the CPU. CPU only needs to specify a sequence of I/o activity to I/o processor. Then, I/o processor executes the necessary I/o instructions which are required for the task, and interrupts the CPU only after the entire sequence of I/o activity as specified by CPU have been completed. An advanced I/o activity as specified by CPU has been completed. An advanced I/o processor can have its own memory. An I/o processor has the additional ability to execute I/o instructions, which provide it’s a complete control of I/O operations. The architecture of I/O processor is shown below.
For high-speed devices a selector channel is used. This channel can transfer data from one high-speed device at a time. I/o modules can handle each of these high-speed devices. Therefore, I/o processors have taking the place of CPU in controlling various I/o modules.
The communication between I/o processor and CPU can be achieved by writing messages in the memory area shared by both the processors. CPU instructs I/o processor to execute an I/o program in the memory. Then the program will specify the device or devices and the area of the memory where the I/o data is stored, or to be stored.
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What happens when multiple interrupt occurs simultaneously? what is an Interrupt Vector? How are the interrupt recognized in microcomputers?
What happens when multiple interrupt occurs simultaneously? what is an Interrupt Vector? How are the interrupt recognized in microcomputers?
Ans An interrupt is a request from Vo or other devices to a processor for service or attention. An interrupt is any exceptional even that causes CPU to temporarily transfer its control from currently executing program to a different program which provide service to the exceptional event. Interrupts are generated for a variety of reasons usually related to the services related to external devices connected to the machine. Multiple interrupt may occurs simultaneously.
Multiple interrupt occurs when any currently executing program is interrupted by another program or process. If a program from a communication line and on another side may receive an instruction it is printing results, the printer on completion of every print operation will generate An interrupt, while the communication1ine controller will be generating the interrupt on arrival of a unit of data. Since, these two interrupts are independent, hence, the communication interrupt may occur while the printer interrupt is being processed. Multiple interrupts are handled in sequential order.
The scheme that can handle multiple interrupt at a time is to disable interrupts. If an interrupt occur while the first interrupt is being processed them it will remain pending, till the interrupts have been enable again. Therefore, in this scheme, the first few instructions in the processing of an interrupt disables other interrupts. After the interrupt service program for the current interrupt is completed, then the processor enables the interrupt and checks whether any other interrupt has occurred. Hence in this approach interrupts are handled in sequential order.
Depending upon the type of service desired, the interrupts are given a type. The service in the form of a procedure is called the interrupt service routine. In case, the first burst of data input is not processed before the second burst arrives, the data may be lost. When the CPU knows that an interrupt has occurred then the CPU execute an interrupt servicing program to service the interrupt.
Interrupt Vector: - The CPU processes on interrupt instruction using the interrupt vector Table (IVT). It is situated in the first 1k byte of memory and has a total of 256 entries each of 4 bytes. The entry in the IVT is identified by the number given in the interrupt instruction and points to an operating system subroutine. The actual address in this table varies from machine to machine. The device, which has made the interrupt request grabs the signal and responds by putting a word, which is an address of interrupt servicing program. This word is called on Interrupt Vector. This address is used for selecting an appropriate interrupt-servicing program.
A microcomputer has a programmable large-scale integrated microprocessor containing all the elements required to process binary encoded data. Providing a control line can interrupt the processor. This line connects the source of interrupts! to the processor. Then interrupt signal is stored in a register of the processor. This register is tested time to time by the processor to determine the occurrence of an interrupt. Once the processor known that an interrupt has occurred then the processor need to execute an Interrupt servicing program which tries to remove the condition which has caused the interrupt. The processor is assigned the address of the interrupt servicing program to be executed. The execution of an instruction in the processor is done using certain set of registers and their respective circuit. The essential context of the processor is saved either into a special save are in main memory or into a stack at the beginning of interrupt processing. This context is restored when the interrupt service program is finished therefore, the interrupted program execution can be restarted from the point of interruption. The instruction execution resumes as soon as the interrupt processing is completed. Therefore, the user instruction need not contain any special code for interrupt handling. This job lies with the processor and the operating system which are also responsible for suspending the execution of the user instruction and after interrupt handing resumes the user instruction from same point.
Ans An interrupt is a request from Vo or other devices to a processor for service or attention. An interrupt is any exceptional even that causes CPU to temporarily transfer its control from currently executing program to a different program which provide service to the exceptional event. Interrupts are generated for a variety of reasons usually related to the services related to external devices connected to the machine. Multiple interrupt may occurs simultaneously.
Multiple interrupt occurs when any currently executing program is interrupted by another program or process. If a program from a communication line and on another side may receive an instruction it is printing results, the printer on completion of every print operation will generate An interrupt, while the communication1ine controller will be generating the interrupt on arrival of a unit of data. Since, these two interrupts are independent, hence, the communication interrupt may occur while the printer interrupt is being processed. Multiple interrupts are handled in sequential order.
The scheme that can handle multiple interrupt at a time is to disable interrupts. If an interrupt occur while the first interrupt is being processed them it will remain pending, till the interrupts have been enable again. Therefore, in this scheme, the first few instructions in the processing of an interrupt disables other interrupts. After the interrupt service program for the current interrupt is completed, then the processor enables the interrupt and checks whether any other interrupt has occurred. Hence in this approach interrupts are handled in sequential order.
Depending upon the type of service desired, the interrupts are given a type. The service in the form of a procedure is called the interrupt service routine. In case, the first burst of data input is not processed before the second burst arrives, the data may be lost. When the CPU knows that an interrupt has occurred then the CPU execute an interrupt servicing program to service the interrupt.
Interrupt Vector: - The CPU processes on interrupt instruction using the interrupt vector Table (IVT). It is situated in the first 1k byte of memory and has a total of 256 entries each of 4 bytes. The entry in the IVT is identified by the number given in the interrupt instruction and points to an operating system subroutine. The actual address in this table varies from machine to machine. The device, which has made the interrupt request grabs the signal and responds by putting a word, which is an address of interrupt servicing program. This word is called on Interrupt Vector. This address is used for selecting an appropriate interrupt-servicing program.
A microcomputer has a programmable large-scale integrated microprocessor containing all the elements required to process binary encoded data. Providing a control line can interrupt the processor. This line connects the source of interrupts! to the processor. Then interrupt signal is stored in a register of the processor. This register is tested time to time by the processor to determine the occurrence of an interrupt. Once the processor known that an interrupt has occurred then the processor need to execute an Interrupt servicing program which tries to remove the condition which has caused the interrupt. The processor is assigned the address of the interrupt servicing program to be executed. The execution of an instruction in the processor is done using certain set of registers and their respective circuit. The essential context of the processor is saved either into a special save are in main memory or into a stack at the beginning of interrupt processing. This context is restored when the interrupt service program is finished therefore, the interrupted program execution can be restarted from the point of interruption. The instruction execution resumes as soon as the interrupt processing is completed. Therefore, the user instruction need not contain any special code for interrupt handling. This job lies with the processor and the operating system which are also responsible for suspending the execution of the user instruction and after interrupt handing resumes the user instruction from same point.
What are the advantages of L1 and L2 Cache memories? Describe the Set Associative Cache mapping scheme.
What are the advantages of L1 and L2 Cache memories? Describe the Set Associative Cache mapping scheme.
Answer:
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In the above architecture the Data-caches is shown as split-caches with two levels LI and L2. The I-Cache stands for instruction cache. PA means physical addressing, VA = virtual addressing, D -Data and I = Instruction. In the above diagram the first level LI cache uses 64KB ofWT D-cache. The second level L2 uses 256KB of WB D-cache.
The main advantage of multi-level cache is faster access, as by inclusion property; the first-level cache is always a subset of the second-level cache. If the hardware consistency is maintained between two cache levels, the efficiency of this multi-level cache organisation is comparatively improved.
The major advantages of multi-level caches include.
• No need to perform cache flusing.
• No aliasing problems.
• Fewer cache bugs in 0.5 kernels.
• When it is used in unix environment no Hushing to data caches is needed if bus watching is provided to monitor the system bus for DMA requests from I/o devices or from other CPUs.
Set Associative Cache Mapping Scheme :
In this mapping each word of cache can store two or more words of memory under the same index address. Each data word is stored together with its tag and the number of tag word item in one word of cache is said to form a set. A set associative cache of set size K will accommodate K words of main memory in each word of cache. Set associative cache offers the best performance cost ratio.
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Most high-performance computer systems are based on this scheme. A set associative cache of set size K is called K-way associative cache. In a k-way associative cache, the m cache block frames are divided into V = m/k sets, .with k blocks per set. Each set is identified by a d-bet set number, where 2-= V. The cache block tags are no reduced to s-d bets. The set size k, is chosen as 2, 4, 8, 16 or 64 depending on a tradeoff among block size. W, cache size m, and other cost factors. A two-way associative cache with four sets is shown above.
Advantages of set-associative cache scheme :
• The block replacement algorithm needs to consider only a few blocks in the same set. Hence, the replacement policy can be more economically implemented with limited choices.
• The k-ways associative search is easier to implement
• Many design tradeoffs can be considered to yield a higher hit ratio on the cache. Often the cache operation is used together with TLB (Translation Lookaside Buffer)
Answer:
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In the above architecture the Data-caches is shown as split-caches with two levels LI and L2. The I-Cache stands for instruction cache. PA means physical addressing, VA = virtual addressing, D -Data and I = Instruction. In the above diagram the first level LI cache uses 64KB ofWT D-cache. The second level L2 uses 256KB of WB D-cache.
The main advantage of multi-level cache is faster access, as by inclusion property; the first-level cache is always a subset of the second-level cache. If the hardware consistency is maintained between two cache levels, the efficiency of this multi-level cache organisation is comparatively improved.
The major advantages of multi-level caches include.
• No need to perform cache flusing.
• No aliasing problems.
• Fewer cache bugs in 0.5 kernels.
• When it is used in unix environment no Hushing to data caches is needed if bus watching is provided to monitor the system bus for DMA requests from I/o devices or from other CPUs.
Set Associative Cache Mapping Scheme :
In this mapping each word of cache can store two or more words of memory under the same index address. Each data word is stored together with its tag and the number of tag word item in one word of cache is said to form a set. A set associative cache of set size K will accommodate K words of main memory in each word of cache. Set associative cache offers the best performance cost ratio.
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Most high-performance computer systems are based on this scheme. A set associative cache of set size K is called K-way associative cache. In a k-way associative cache, the m cache block frames are divided into V = m/k sets, .with k blocks per set. Each set is identified by a d-bet set number, where 2-= V. The cache block tags are no reduced to s-d bets. The set size k, is chosen as 2, 4, 8, 16 or 64 depending on a tradeoff among block size. W, cache size m, and other cost factors. A two-way associative cache with four sets is shown above.
Advantages of set-associative cache scheme :
• The block replacement algorithm needs to consider only a few blocks in the same set. Hence, the replacement policy can be more economically implemented with limited choices.
• The k-ways associative search is easier to implement
• Many design tradeoffs can be considered to yield a higher hit ratio on the cache. Often the cache operation is used together with TLB (Translation Lookaside Buffer)
What should be the characteristics of hard disk drive that is to be used for keeping the Airline reservation database.
What should be the characteristics of hard disk drive that is to be used for keeping the Airline reservation database. Assume that there is a centralized database that stores the information about all the flight reservations. Give reasons in support of your.
Answer: -
Hard disk drive is handled by the OS with limited user intervention. The disk storages considered the highest level of on-line memory. It holds the system programs such as the OS and compilers and some user programs and their data sets. It holds copies of present and past user programs and processed results and files. A typical centralized computer has the chache and main memory on a processor board and hard disks in an attached disk drive.
The Airline Reservation Database can occupy more space on the hard disk drive. Because database is centralizing, the capacity of the hard disk drive is too large. The hard disk drive consists of a motor to rotate the disk peak about its axis at a minimum speed of 3600 rps and maximum speed of 7200 rps. The hard disk drive has a set of magnetic heads mounted on arms.
Characteristics of hard disk drive : The characteristics of hard disk drive that is to be used for keeping the Airline reservation database (centralized) can be classified as following :
1) For fixed head, one read/write head per track is required. Heads can be mounted on a arm which extends to the centre of the disk. On the movable head disk one read/write head, which is fitted on an arm, is required. This arm allows head to position on any track of the platter.
2) The hard disks are normally mounted in a disk drive which consists of an arm and a shaft along with the electronic circuity for input-output of data. The disk rotates along with the shaft The hard disk is permanently mounted on the disk drive.
3) The magnetized coating is applied to both the sides of the platter in the hard disk drive. The data can be recorded on either side of this disk.
4) Hard disks have multiple platters stacked vertically at a distance of an inch. This is called disk pack. Disk pack contains cylinder which is the ring of all co-centric tracks. A disk pack can contain multiple heads mounted with the same arm.
5) The read/write heads are placed at a fixed distance from the platter, allowing an air gap. The gap of platter and head plays an important role. The smaller the size of the head the closer it should be to the platter surface in order to read and write properly. A smaller head allows greater data density on the disk.
6) Hard disk operate in semi-random mode of operation and normally are referenced block wise The data access time on hard disk has two components : Seek time (time to position the head on a specific track) and latency time (time required by a sector to reach below the read/write head).
Reasons:
1. The growth of processor speed has outstripped the growth in disk speed. This imbalance transforms traditionally CPU-bound applications to disk I/o bound applications. To obtain an improvement in application performance disk I/o bandwidth must be increased. The most common way to do this is by increasing the number of disk used to work on the problem.
2. Arrays of small diameter disks often have substantial cost power and performance advantages over large disk drives.
3. Disk array subsystems can be made highly reliable by storing a small amount of redundant information in the array without this redundancy, large disk arrays have unacceptably low data reliability because of their large number of components disks.
Redundant array of Inexpensive Disk (RAID) is used for a database server like Airline reservation database. RAID system balance load across a set of spindles providing a measure of automatic load balancing. When a single disk drive in a RAID array fails, the RAID system can recover the data without any need to resort to restoring a backup. These advantages come at some cost in terms of storage efficiency and performance, the deminent forms of RAID are RAID 5 and RAID 0.1.
For a database like Airline reservation databse, I would recommend minimum size of hard disk of 40 GB and the minimum size of cache of 512 KB.
Answer: -
Hard disk drive is handled by the OS with limited user intervention. The disk storages considered the highest level of on-line memory. It holds the system programs such as the OS and compilers and some user programs and their data sets. It holds copies of present and past user programs and processed results and files. A typical centralized computer has the chache and main memory on a processor board and hard disks in an attached disk drive.
The Airline Reservation Database can occupy more space on the hard disk drive. Because database is centralizing, the capacity of the hard disk drive is too large. The hard disk drive consists of a motor to rotate the disk peak about its axis at a minimum speed of 3600 rps and maximum speed of 7200 rps. The hard disk drive has a set of magnetic heads mounted on arms.
Characteristics of hard disk drive : The characteristics of hard disk drive that is to be used for keeping the Airline reservation database (centralized) can be classified as following :
1) For fixed head, one read/write head per track is required. Heads can be mounted on a arm which extends to the centre of the disk. On the movable head disk one read/write head, which is fitted on an arm, is required. This arm allows head to position on any track of the platter.
2) The hard disks are normally mounted in a disk drive which consists of an arm and a shaft along with the electronic circuity for input-output of data. The disk rotates along with the shaft The hard disk is permanently mounted on the disk drive.
3) The magnetized coating is applied to both the sides of the platter in the hard disk drive. The data can be recorded on either side of this disk.
4) Hard disks have multiple platters stacked vertically at a distance of an inch. This is called disk pack. Disk pack contains cylinder which is the ring of all co-centric tracks. A disk pack can contain multiple heads mounted with the same arm.
5) The read/write heads are placed at a fixed distance from the platter, allowing an air gap. The gap of platter and head plays an important role. The smaller the size of the head the closer it should be to the platter surface in order to read and write properly. A smaller head allows greater data density on the disk.
6) Hard disk operate in semi-random mode of operation and normally are referenced block wise The data access time on hard disk has two components : Seek time (time to position the head on a specific track) and latency time (time required by a sector to reach below the read/write head).
Reasons:
1. The growth of processor speed has outstripped the growth in disk speed. This imbalance transforms traditionally CPU-bound applications to disk I/o bound applications. To obtain an improvement in application performance disk I/o bandwidth must be increased. The most common way to do this is by increasing the number of disk used to work on the problem.
2. Arrays of small diameter disks often have substantial cost power and performance advantages over large disk drives.
3. Disk array subsystems can be made highly reliable by storing a small amount of redundant information in the array without this redundancy, large disk arrays have unacceptably low data reliability because of their large number of components disks.
Redundant array of Inexpensive Disk (RAID) is used for a database server like Airline reservation database. RAID system balance load across a set of spindles providing a measure of automatic load balancing. When a single disk drive in a RAID array fails, the RAID system can recover the data without any need to resort to restoring a backup. These advantages come at some cost in terms of storage efficiency and performance, the deminent forms of RAID are RAID 5 and RAID 0.1.
For a database like Airline reservation databse, I would recommend minimum size of hard disk of 40 GB and the minimum size of cache of 512 KB.
WRITE A PROGRAM IN 8086 that accepts two floating point number form the correctly the format.
WRITE A PROGRAM IN 8086 that accepts two floating point number form the correctly the format.
Print macro msg
Mov ah, 09h
Mov dx , offset msg
Int 21h
End
DATA SEGEMENT
NUM1 DB 100 DUP(0)
NUM2 DB 100 DUP(0)
MSG1 DB “ ENTER THE FIRST NUMBER”
MSG2 DB “ENTER THE SECOND NUMBER”
MSG3 DB “ SUM OF TWO NUMBER”
MSG4 DB “ EXPONENT IS NOT EQUAL”
RES DB 100 DUP (0)
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE, DS : DATA
START
MOV AX,DATA
MOV DS,AX
PRINT MSG2
MOV SI, OFFSET NUM1
X: MOV AH,02H
INT 21H
MOV [SI],AL
INC SI
CMP AL,0DH
JNE X
PRINT MSG2
MOV SI, OFFSET NUM2
Y:
MOV AH, 01H
INT 21H
MOV [SI],AL
INC SI
CMP AL, 0DH
JNE Y
W: MOV CL,03H
MOV SI,OFFSET NUM1
MOV DI,OFFSET NUM2
ADD SI, 07H
ADD DI,07H
MOV AL, [SI]
MOV BL,[DI]
COM AL, BL
INC SI
INC DI
JNE
LOOP W
MOV CL,04H
XY: MOV BX,OFFSET RES
MOV SI, OFFSET NUM1
MOV DI, OFFSET NUM2
MOV AL,[SI]
ADD AL,[DI]
MOV [BX],AL
INC SI
INC DI
INC BX
LOOP XY
RCL AL,01H
AND AL,01H
MOV [BX], AL
PRINT MSG3
PRINT RES
MOV AH,09CH
INT 21H
CODE ENDS
END START
PRINT MSG 4
MOV AH, 4CH
INT 21H
ALGORITHM
Step 1: start
Step 2: input number 1 and number2
Step3: n1=last character of number 1
N2=last character of number2
Step4: take a counter c and I=0
Step compare n1 and n2 of both are same go to step 6
Else
Go to step 11
Steps 6: n1= n1-1 and n2= n2-1
C=c+1
C=3 then go to step 7
Step 7
Take n1= 4th character of numebr1
And 4th character of number 2
C= 1
Step 8:
Add n1 and n2 , sum stored in variable s and carry stand in CA.
Step 9:
C=n+1
N1=n1-1 and n2=n2-1
Step 10
If c=5 the n go to step 12
Else
Go to step 8
Step 11: print “ exponent not match”
Step 12: print “ sum of two number”
Step 13: end
Print macro msg
Mov ah, 09h
Mov dx , offset msg
Int 21h
End
DATA SEGEMENT
NUM1 DB 100 DUP(0)
NUM2 DB 100 DUP(0)
MSG1 DB “ ENTER THE FIRST NUMBER”
MSG2 DB “ENTER THE SECOND NUMBER”
MSG3 DB “ SUM OF TWO NUMBER”
MSG4 DB “ EXPONENT IS NOT EQUAL”
RES DB 100 DUP (0)
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE, DS : DATA
START
MOV AX,DATA
MOV DS,AX
PRINT MSG2
MOV SI, OFFSET NUM1
X: MOV AH,02H
INT 21H
MOV [SI],AL
INC SI
CMP AL,0DH
JNE X
PRINT MSG2
MOV SI, OFFSET NUM2
Y:
MOV AH, 01H
INT 21H
MOV [SI],AL
INC SI
CMP AL, 0DH
JNE Y
W: MOV CL,03H
MOV SI,OFFSET NUM1
MOV DI,OFFSET NUM2
ADD SI, 07H
ADD DI,07H
MOV AL, [SI]
MOV BL,[DI]
COM AL, BL
INC SI
INC DI
JNE
LOOP W
MOV CL,04H
XY: MOV BX,OFFSET RES
MOV SI, OFFSET NUM1
MOV DI, OFFSET NUM2
MOV AL,[SI]
ADD AL,[DI]
MOV [BX],AL
INC SI
INC DI
INC BX
LOOP XY
RCL AL,01H
AND AL,01H
MOV [BX], AL
PRINT MSG3
PRINT RES
MOV AH,09CH
INT 21H
CODE ENDS
END START
PRINT MSG 4
MOV AH, 4CH
INT 21H
ALGORITHM
Step 1: start
Step 2: input number 1 and number2
Step3: n1=last character of number 1
N2=last character of number2
Step4: take a counter c and I=0
Step compare n1 and n2 of both are same go to step 6
Else
Go to step 11
Steps 6: n1= n1-1 and n2= n2-1
C=c+1
C=3 then go to step 7
Step 7
Take n1= 4th character of numebr1
And 4th character of number 2
C= 1
Step 8:
Add n1 and n2 , sum stored in variable s and carry stand in CA.
Step 9:
C=n+1
N1=n1-1 and n2=n2-1
Step 10
If c=5 the n go to step 12
Else
Go to step 8
Step 11: print “ exponent not match”
Step 12: print “ sum of two number”
Step 13: end
WAP in 8086 that can be used for password matching.
WAP in 8086 that can be used for password
matching.
;ABSTRACT : this program inputs a password
;registers used : CS,DS,ES,AX,DX,CX,SI,DI
;port used : fffah
;PROCEDURES : None used
DATA_HERE SEGMENT
PASSWORD DB ‘FAILSAFE’
INPUT_WORD DB 8 DUP(?) ; SPACE FOR USER INPUT
DATA_HERE ENDS
CODE_HERE SEGMENT
ASSUME CS:CODE_HERE,DS:DATA_HERE,
ES:DATA_HERE
MOV AX,DATA_HERE
MOV DS,AX
MOV ES,AX
MOV DX,OFFFEH
AL,99H
OUT DX,AL
LEA SI,PASSWORD
LEA DI, INPUT_WORD
MOV CX,O8H
CLD
REPE CMPSB
JNE SOUND_ALARM
JMP OK
SOUND_ALARM:
MOV AL,01
MOV DX,0FFFAH
OUT DX,AL
HLT
OK: NOP
CODE_HERE ENDS
END
matching.
;ABSTRACT : this program inputs a password
;registers used : CS,DS,ES,AX,DX,CX,SI,DI
;port used : fffah
;PROCEDURES : None used
DATA_HERE SEGMENT
PASSWORD DB ‘FAILSAFE’
INPUT_WORD DB 8 DUP(?) ; SPACE FOR USER INPUT
DATA_HERE ENDS
CODE_HERE SEGMENT
ASSUME CS:CODE_HERE,DS:DATA_HERE,
ES:DATA_HERE
MOV AX,DATA_HERE
MOV DS,AX
MOV ES,AX
MOV DX,OFFFEH
AL,99H
OUT DX,AL
LEA SI,PASSWORD
LEA DI, INPUT_WORD
MOV CX,O8H
CLD
REPE CMPSB
JNE SOUND_ALARM
JMP OK
SOUND_ALARM:
MOV AL,01
MOV DX,0FFFAH
OUT DX,AL
HLT
OK: NOP
CODE_HERE ENDS
END
Most of the recent processor has cache memory of 128 KB or more.
Most of the recent processor has cache memory of 128 KB or more.
Solution:-
The evolution of cache organization is seen clearly in the evolution of Intel microprocessors. The 80386 does not include an on –chip cache. The 80486 includes a single on-chip cache of 8 KB. Using a line size of 16 Bytes and four-way set associative organization. All of the Pentium processors include two on-chip L1 chances, one for data and one for instructions. For the Pentium 4, the l1 cache is 8 KB, using a line size 64 KB and a four-way set associative organization. The Pentium 4 Instruction cache is described subsequently . the Pentium 4 also includes an l2 cache that feeds both of the l1 cache. The l2 cache is eight-way set associative with a size of 256KB and a line size of 128 Bytes.
Cache Organization
The PowerPC cache organization has evolved with the overall arcxhitecture of the PowerPC family, eflecting the relentless pursuit of performance that is the driving force for all microporessor designers.
The original mode, the 601, includes a signle code/data 32-KB. Cache that is eight-way set associative. The 603 employs a more sophisticated RISC design but has a smaller cache , 16 KB divided into separate instruction and data caches, both using two-way set associative organization. The result is that the 603 gives approximately the same performance as the 601 at lower cost. The 604 and 620 each doubled the sized of the caches from preceding model. The G3 and G4 modles has the same size L1 caches as the 620.
The L1 caches are eight-way set associative. The L2 cache is a two-way set associative cache with 256KB,512Kb,or 1 MB of memory.
Solution:-
The evolution of cache organization is seen clearly in the evolution of Intel microprocessors. The 80386 does not include an on –chip cache. The 80486 includes a single on-chip cache of 8 KB. Using a line size of 16 Bytes and four-way set associative organization. All of the Pentium processors include two on-chip L1 chances, one for data and one for instructions. For the Pentium 4, the l1 cache is 8 KB, using a line size 64 KB and a four-way set associative organization. The Pentium 4 Instruction cache is described subsequently . the Pentium 4 also includes an l2 cache that feeds both of the l1 cache. The l2 cache is eight-way set associative with a size of 256KB and a line size of 128 Bytes.
Cache Organization
The PowerPC cache organization has evolved with the overall arcxhitecture of the PowerPC family, eflecting the relentless pursuit of performance that is the driving force for all microporessor designers.
The original mode, the 601, includes a signle code/data 32-KB. Cache that is eight-way set associative. The 603 employs a more sophisticated RISC design but has a smaller cache , 16 KB divided into separate instruction and data caches, both using two-way set associative organization. The result is that the 603 gives approximately the same performance as the 601 at lower cost. The 604 and 620 each doubled the sized of the caches from preceding model. The G3 and G4 modles has the same size L1 caches as the 620.
The L1 caches are eight-way set associative. The L2 cache is a two-way set associative cache with 256KB,512Kb,or 1 MB of memory.
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