Saturday, May 30, 2009

Matrix multiplication

Write a program in 8086 assembly language that multiplies two 2*2 matrices to create a third matrix of size (2*2). Make suitable assumptions, if any. Properly document the program.

Solution.

;
; BUILD - TASM MATMUL.ASM
; TLINK MATMUL
;
; USAGE - MATMUL

READNUM MACRO NUM
PUSH AX
PUSH BX
MOV AH, OLH ;GET CHAR FROM KEYBOARD INT 21H CALL DOS SERVICE
SUB AL, ‘0’ ;ASCII NUM TO DECIMAL
MOV BH, OAH
MUL BH MULTIPLY BY 10
MOV NUM, AL STORE FIRST DIGIT IN NUM
MOV AH, OLH GET CHAR FROM KEYBOARD
INT 21H CALL DOS SERVICE
SUB AL, ‘0’ ASCII NUM TO DECIMAL
ADD NUM , AL ADD SECOND DIGIT
POP BX
POP AX
ENDM
PRINTSTRING MACRO MSG ;PRINTSTRING – THE USER
DEFINED MACRO
MOV AH, 09H DISPLAY STRING FUNCTION
MOV DX, OFFSET MSG ;INITIALIZE DX TO MSG
INT 21H CALL DOS SERVICE

_DATA SEGMENT _DATA – NAME OF USER DEFINED SEGMENT

CREQU 0DB ASCII CODE FOR CARRIAGE
RETURN
LF EQU OAH ;ASCII CODE FOR LINE FEED
M EQU 3 ;ORDER OF MATRIX
MSG DB ‘PROGRAM FOR FINDING THE PRODUCT OF MATRICES(M X M)$’
MSGO DB CR,LF,’ENTER ELEMENTS OF MATRIX A IN ROW MAJOR…$’
MSGL DB CR,LF,’ENTER ELEMENTS OF MATRIX B IN ROW MAJOR…$’
MSG2 DB CR,LF,’ELEMENT:’,‘$’
MSG3 DB CR,LF,’PRODUCT MATRIX’
C=A*B…….’, ‘$’
;VARIABLES FOR MATRIX MANIPULATION
MATA DB 20 DUP(0)
MATB DB 20 DUP(0)
MATC DB 20 DUP(0)
NEWLINE DB CR, LF, ‘$’

SPACE DB ‘$’
MATRIX OPERATION INDEX VARIABLES
I DB?
J DB?
K DB?
RESULT DB 5 DUP(0)
TNUM DB?
_DATA ENDS ;END OF _DATA SEGMENT

_CODE SEGMENT
;INITIALIAZE CS, DS
ASSUME CS: CODE, DS: _DATA
START: MOV AX, _DATA ;INITIALIZE OS TO THE
DATA SEGMENT
MOV DS, AX
PRINTSTRING MSG
;READ MATRIX A
PRINT STRING MSG0
;PUT ALL INPUT PARAMETERS ONTO THE STACK IN REVERSE ORDER
MOV AL, M
PUSH SI
CALL READMATRIX
ADD SP,4
PUSH OPERATIONS
;READ MATRIX B
PRINTSTRING MSGL

;PUT ALL INPUT PARAMETERS ONTO THE STACK IN REVERSE
ORDER
MOV AL,M
PUSH AX
MOV SI, OFFSET MATB
PUSH SI
CALL READMATRIX
ADD SP,4 ;ADJUST STACK FOR TWO PUSH OPERATIONS

;MAT C=MATA*MATB
;PUT ALL INPUT PARAMETERS ONTO THE STACK IN REVERSE ORDER

PRINTSTRING MSG3
MOV AL,M
PUSH AX,
MOV AX, OFFSET MATC
PUSH AX
MOV AX, OFFSET MATB
PUSH AX
MOV AX, OFFSET MATA
PUSH AX
CAL MULTIMATRIX
ADD SP,8 :ADJUST STACK FOR FOUR PUSH
OPERATION
MOV AL,M
PUSH AX
MOV SI, OFFSET MATC
PUSH SI
CALL PRINTMATRIX
ADD SP,4 ;ADJUST STACK FOR TWO PUSH OPERATION
MOV AH,4CH ;PROGRAM TERMINATE FUNCTION
MOV AL, 00H ;RETURN CODE
FOR ERROR LEVEL SETTING
INT 21 H ;CALL DOS SERVICE
;MACRO: MELEADDR
;LOGIC
;ADDR = ADDR(MAT)+J+(I-I)*ORDER
;RETURNS:
;BX-EFFECTIVE ADDRESS OF AN ELEMENT

MELEADDR MACRO MAT,I,J,ORDER

PUSH AX
MOV AL,I
DEC AL
MOV AH,00 ;AX = (I-I)
MOV BI, ORDER ;AX = (I-I)*ORDER
NUL BI
ADD AI,J
MOV BX,MAT
ADD BX,AX

(I-I)* ORDER

POP AX
ENDM

;MULTIMATRIX (A,B,C ORDER)
;C=A*B

MULTIMATRIX PROC NEAR
PUSH BP
MOV BP,SP ;MAKE STACK
ADDRESSABLE
PUSH SI
PUSH DI
PUSH CX
PUSH BX
PUSH AX
MOV SI, [BP+4] ; MATRIX A
MOV DI, [BP+6] ;MATRIX B
MOV BX,[BP+8] ; MATRIX C
MOV DX, [BP+10] ;ORDER OF MATRIX. USE
LOWER BYTE
;DL-ORDER OF THE MATRIX

MOV A1,01
MOV I, A1 ;I=1

MNEXTI:
MOV A1,01
MOV J1, A1 ;J=1
MNEXTJ:
MOV A1,01
MOV K, 01 ;K=1
MOV CL, 00 ;C[I][J]=0
MNEXTK:
MEMEADDR [BP+4],I,K,DL
MOV AH,00
MOV AL,[BX] ;AL=B[I][K]
MELEADDR [BP+6],K,J,DL
MUL BYTE PTR [BX] ;AX = B[I][K]
ADD CL,AL
C[I][J]=C[I][J]+B[I][K]*C[K][J]
;K=K+1
MOV AL,K
INC AL
MOV K,AL
CMP AL,DL
JLE MNEXTK ;REPEAT FOR K <= ORDER
MELEADDR [BP+8],I,J,DL
MOV [BX],CL ;PUT C[I][J] INTO C MATRIX

;J=J+1
MOV AL,J
INC AL
MOV J,AL
CMP AL,DL
JLE MNEXTI ;REPEAT FOR I ,= ORDER

POP AX ;RESTORE
REGISTERS
POP BX
POP CX
POP DI
POP SI
POP BP
RET
MULTIMATRIX ENDP

;FUNCTION: READ MATRIX (MATRIX, ORDER OF MATRIX)
;INPUT:
;PUT PARAMETERS INTO THE STACK IN REVERSE ORDER
;RETURNS:
; MATRIX

READMATRIX PROC NEAR
PUSH BP
MOV BP,SP ;SAVE REGISTERS
ADDRESSABLE
PUSH BX
PUSH AX
MOV SI, [BP+4] ;POINTER TO THE MATRIX

MOV AX, [BP+6] ;ORDER OF MATRIX
MOV CH, AL ;CH=I INDEX CONTROL
NEXTI:
MOV AX, [BP+6] ;CL=J INDEX CONTROL
MOV CL, AL
NEXTJ:
INC SI ;INDEX FOR NEXT ELEMENT
PRINTSTRING MSG2
READNUM TNUM ;READ NUMBER
MOV AL, TNUM ;STORE INTO AL
MOV [SI], AL ;STORE NUMBER INTO TABLE
DEC CL ;REPEAT FOR ALL
JNZ NEXTJ COLUMNS
DEC CH ;REPEAT FOR ALL ROWS
POP AX ;RESTORE THE REGISTERS
POP BX
POP BP
RET
READMATRIX ENDP
FUNCTION: PRINTMATRIX(MATRIX, ORDER OF MATRIX)
PRINTMATRIX PROC NEAR
PUSH BP
MOV BP, SP MAKE STACK ADDRESABLE
PUSH BX
PUSH AX
MOV SI, [BP+4] SI=POINTER TO MATRIX
MOV SI, [BP+6] ORDER OF MATRIX
MOV CH, AL CH=I INDEX CONTROL

PNEXTI:
PRINTSTRING NEW LINE
MOV AX, [BP+6]
MOV CL, AL ` ;CL=J INDEX CONTROL
PNEXTJ:
INC SI ;INDEX FOR NEXT ELEMENT
;DISPLAY ELEMENT
PUSH SI
MOV AH, 0 ;AX,=MAT[I][J]
MOV AL, BYTE PTR [SI]
MOV SI, OFFSET RESULT
CALL HEX2ASC
PRINTSTRING RESULT
PRINTSTRING SPACE
POP SI
DEC CI
JNZ PNEXTJ ;REPEAT FOR ALL COLUMNS
DEC CH
JNZ PNEXTI ;REPEAT FOR ALL ROWS
POP AX ;RESTORE REGISTERS
POP BX
POP BP
RET

PRINTMATRIX ENDP
;FUNCTION TO CONVERT HEXADECIMAL NUMBER TO ASCII STRING
;AX – INPUT NUMBER
;SI – POINTER TO RESULT STORAGE AREA

HEX2ASC PROC NEAR
PUSH AX ;SAVE REGISTERS
PUSH BX
PUSH CX
PUSH DX
PUSH SI
MOV CX, 00H ;COUNTER FOR INTERMEDIATE DATA PUSHED

MOV BX,OAH ;LOAD 10 IN BL
RPTL:
MOV DX, 00
DIV BX ;DIVIDE NUM BY 10
ADD DL, ’0’ ;CONVERT REMAINDER TO ASCII
PUSH DX ;STORE ASCII DIGIT ONTO THE STACK
INC CX ;UPDATE COUNTER

CMP AX, 0AH ;IS NUM LESS THAN OR EQUAL TO 10
JGE RPTL

ADD AL, ‘0’
MOV [SI], AL
;POP ALL INTERMEDIATE DATA FROM STACK AND STORE IN RESULT RPT2:
POP AX ;POP DATA
INC SI ;ADVANCE RESULT STRING POINTER
MOV [SI], AL ;STORE IN RESULT
LOOP RPT2

INC SI
MOV AL, ‘$’
MOV [SI], AL ;APPEND END OF STRING

POP SI ;RESTORE THE REGISTERS
POP DX
POP CX
POP BX
POP AX
RET

HEX2ASC ENDP
_CODE ENDS ;END OF SEGMENT
END START ;END OF PROGRAM

Program in 8086 assembly language that concatenates two given string to create a third string.

Write a program in 8086 assembly language that concatenates two given string to create a third string.


DATA SEGMENT
BITVAL DW 0921H,0825H,0804H,0972H
WORD1 Dw 3 dup(0000h)
ASCIINUM DB 13 DUP(‘0’)
OUTLOOPCNT BE ?
DATA ENDS

CODE SEGMENT
ASSUME CS: CODE,DS:DATA

START:
MOVE AX,DATA
MOV SI,00H
MOV DI,OOH
MOVE AX, BITVAL[SI]
MOV CL,04
SHL AX,CL
SHR AL, CL
MOV BH,AL
ADD SI,02
MOV DX,BITVAL[SI]
MOV BL,DH
SHL BL,CL
SHL BX,CL
MOV AL,BH
MOV WORD1[DI],AX
ADD DI,02

MOV AH,DL
ADD SI, 02
MOV DX,BITVAL[SI]
SHL DX,CL
MOV AL,DH
MOV WORD1[DI],AX
ADD DI,02

MOV DX,BITVAL[SI]
MOV AH,DL
ADD SI,02
MOV DX,BITVAL[SI]
MOV BL,DL
SHL DX,CL
MOV ALMDH
SHL AS,CL
MOV AL,BL
MOV WORD1[DI],AX
MOV BX , 00H
MOV SI,00H
LOOP1: MOV AX,WORD1[SI]
MOV AL,AH
MOV CL,02

LOOP 2: MOV OUTLOOPCNT,CL
MOV DL,AL
MOV CL,04
ROR DL,CL
AND DL,0FH
OR DL,30H
MOV ASCIINUM[BX],DL
INC BX
MOV DL,AL
AND DL,0FH
OR DL,30H
MOV ASCIINUM[BX],DL
INC BX
MOV AX,WORD1[SI]
MOV CL,OUTLOOPCNT
LOOP LOOP2
CMP SI,04
JE LOOP3
ADD SI,02
JUMP LOOP1
LOOP3: MOV ASCIINUM[BX],’$’
MOV AH,09H
LEA DX,ASCIINUM
INT 21H
MOV ZX,4C00H
INT 21H

CODE ENDS
END START

Addressing modes of 8086 microprocessor .

Describe the addressing modes of 8086 microprocessor .

The 8086 BIU we described how the 8086 accesses code bytes suing CS and IP. We also described how the 8086 accesses the stack using SS and SP. The different ways that an 8086 can access the data that it operates on. The different ways that a processor can access data are referred to as its addressing modes. In assembly language statement the addressing mode is indicated in the instruction. We will used the 8086 MOV instruction to illustrate some of the 8086 addressing modes.
The Move instruction has the format:-

MOV destination, source

When executed, this instruction copies a word or a byte from the specified source location to the specified destination location. The source can be a number written directly in a instruction, s specified register, or a memory location specified in one of 24 different ways. The destination can be a specified register or a memory location specified in any one of 24 different ways. the source and the destination cannot both be memory locations in an instruction.

Immediate Addressing Mode

Suppose that in a program you need to put the number 437H in te CS register. The MOV CX , 437BH instruction can be used to do this when it executes, this instruction will put the immediate hexadecimal number 437BH in the 16-it CX register. This is referred to as immediate addressing mode because the number to be loaded into the CS register will be put in two memory locations immediately following the code for the MOV instruction. This is similar to the way the port address was put in memory immediately after the code for the input instruction in the three-instruction program in above figure.

Register Addressing Mode

Register addressing mode means that a register is the source of an operand for an
Instruction. The instruction
MOV CS,AX ( example)
Copies the contents of the 16 –bits AX register into the 16 bit CX register. Remember that the Destination location is specified in the instruction before te source. Also not hat the contents of AX are just copied t CX. Not actually moved. In other words, the previous content of CS are written over, but the contents of AX are not changed.

Direct Addressing Mode

For the simplest memory addressing mode the effective address is just an 8 and 16 bit number written directly in the instruction. The instruction MOV CL,[437 AH] is an example . the square brackets around the 437AH are shorthand for “ te contents of the memory location at a displacement from the segment base of “ when executed. This instruction will copy the contents of the memory location, at a displacement of 437 AH from the data segment base, into the CL register. Shifting the data segment base in DS four bits left and adding the effective address 437AH to the result will produce the actual 20-bit pysical memory address. Above figure sows how the operation is done. This addressing mode is called direct because the displacement of operand from the segment base is specified directly in the instruction. The displacement in the instruction will be added to the data segment base in DS unless you used a segment override prefix to tell the BIU to add it to some other segment base.

Addressing Schemes

Addressing schemes is the mechanism employed for specified operands. The arrangements of opcodes and operands and their number within the instruction determine the form or format of instruction. a hypothetical machine which does not have any registers but very large cache and main memory can have the following addressing modes.
1. Immediate Addressing
2. Direct Addressing
3. Indirect Addressing
4. Stack Addressing
(1) Immediate Addressing
Under this scheme actual operand D is A the content of the operand field
D=A
This addressing is used to initialized value of variable requiring no memory access for execution.
(2) Direct addressing
in this the content A of operand field specify effective address of the operand and the next statement below implies the data is stored in the memory location specified by effective address
EA = A, D=(EA)
In this scheme only memory references are required. If the addressing scheme has n bits then address space addressable is 2n memory address.
(3) Indirect addressing:
In this addressing effective address EA and the contents of operand field are related by
EA=(A) , D=(EA)
The disadvanteg of this addressing scheme is that it requires 2 memory references to fetch the effective address from the memory and second for fetching the operand using EA. In this addressing the addressed space is determined by word length.
(4) Stack Addressing:
In this the address of operand is not specified explicitly . it is found on the top of the stack, in the absence of registers we can preserve the top of stack pointer in the memory.
Comment
All the four addressing schemes are using memory locations and not registers their disadvantage is that the addressable memory location is dependent on the instruction code length i.e., if the code is of n bits the addressable memory is 2n
Locations. The other disadvantage is the multiple accesses of locations for fetching a single data.

Interrupt and its use in assembly language

Interrupt:
The interrupt is defined loosely to any exceptional event that causes CPU to temporarily transfer its control from currently executing program to a different program, which provide service to the exceptional event. An interrupt may be generated by a number of sources, which may be either internal or external to the CPU.
OCCURRING:
There is a problem here in the computer’s ability to know when a peripheral device has performed a given operation. Suppose we wish to find some data on a magnetic tape and are unwilling to wait for the tape to be searched, desiring to perform other calculations while waiting. If the computer must continually look to see whether the tape drive now has the data available, then time is lost and programming complexity is increased. To alleviate this, the computer bus is generally provided with control lines which are called interrupt lines, and a peripheral device can raise one of these lines when it has completed an action and is ready for attention.
-------
Interrupt use in Assembly language:
The 8085 has five interrupt signals that cab be used to interrupt a program execution. One of the signals, INTR (interrupt Request), is identical to the 8080A microprocessor interrupt signal (INT) the others are enhancements to the 8080A . the microprocessor acknowledges an interrupt by the ITA ( interrupt acknowledge) signal.
The 8080A interrupt processes controlled by the interrupt Enable flip-flop , which is internal to the processor can be set or reset by using software instructions. If the flip-flop is enabled and the input to the interrupt signal INT (pin 14) goes high, the microprocessor is interrupted. This is a mask able interrupt and can be disabled. The 8080A has only one interrupt signal; it does not have a non mask able interrupt. The 8085 has an interrupt signal called INTR (pin 10) functionally identical with the 8080A interrupt. However, the 8085 has additional interrupt signals as well. To avoid confusion, we will refer to the interrupt process that is common to both the processors as the 8080A interrupt. The best way to describe the 8080A interrupt process is to compare it to a telephone with a blinking light instead of a rig.
The cpu responds to the interrupt signal by storing the return address from the program counter into a memroy stack and then control branches to a service routine the processes the required I/O transfer. The way that the unit to another. In principle , there are two methods for accomplishing this. One is called the branch address is assigned to a fixed location in memory. in a vectored interrupt , the source that interrupts supplies the branch information computers the interrupt vector to the computer. The information is called the interrupt vector.

Write a program in 8086 assembly language that accepts a character string of a maximum size of 10 characters from the keyboard.......

Write a program in 8086 assembly language that accepts a character string of a maximum size of 10 characters from the keyboard; converts each alphabet in the string to upper case and coverts each alphabet to next alphabet, that is, A will be converted to B; B to C, C to D ….and Z to A. The resultant string is output on the monitor. You must run this program.



DATA SEGMENT
STR1 DB 80 DUP (0)
MSG1 DB ‘ENTER A STRIMG $’
CR EQU ODH
PORT DW?

DATA SEGMENT
ASSUME CS: CODE DS: DATA
START:
MOV AX, DATA
MOV DS, AX
MOV DX, OFFSET MSG1
INT 2H ; TO PRINT MSG1
RDCHAR1:
MOV SI, OFFSET STR1 ; READING STRING1
RDCHAR1:
MOV AH, 01
INT 21H
MOV [SI], AL
. INC SI
CMP AL, CR
JNE RDCHAR1
MOV SI, OFFSET STR1
MOV CL, 00
MOV CH, 00

END START

Write a subroutine of 8086 assembly language that coverts a 2 digit number entered by keyboard to equivalent binary in DX register

Write a subroutine of 8086 assembly language that coverts a 2 digit number entered by keyboard to equivalent binary in DX register, provided both the entered digits are numeric. Test this subroutine through an assembly program. The main program must get the result in DX register and put it in a memory location.


DATA SEGMENT
MSG 1 DB ‘ENTER 2 DIGIT NUMBER $’
PORT DW?
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE DS:DATA
START:
MOV AX, DATA
MOV DS, AX
MOV AH, 09H
MOV DX, OFFSET MSG1
INT 21H ; TO PRINT MSG1
MOV AH, 01H
INT 21H
SUB AL, ‘0’
MOV BH, OAH
MVL BH
MOV BL, AL
MOV AH, 01H
INT 21H
SUB AL, ‘0’
ADD BL, AL
OUT PORT, BL

CODE ENDS
END START

Addressing modes required for this machine?

Assume that a machine and its OS does not support stack, but support arrays, subroutine calls with maximum of 2 arguments; and other simple arithmetic, logic and shift instructions. What addressing modes would be required for this machine? Justify your answer.


Machine and its OS support arrays, Subroutines calls with maximum of 2 arguments, such as arithmetic, logic and shift instruments.

Arithmetic Operation:- Almost all the machines provide the four basic arithmetic operations on sign fixed point integer. Some machines provide operation on floating point and packed decimal number.
It arithmetic operations which can be provided in a machine in general are-
ADD, SUBTRACT, MULTIPLY, DIVIDE
ABSOLUTE, NEGATE, INCREMENT, DECREMENT

Logical and Shift Operation:- The logical operations are based an Boolean operation performed an binary data. Some of the logical operations are – AND, OR, NOT Exclusive OR.

Shift Operation:-

* In logical left most right shift the “bitin” is a O bit
*Arithmetic shift is same as logical shift except for the sign bit, which is not shifted.
*A Circular shift uses the “bit out” bit as the “bit in” bit
Subroutine Call:- It is a self user program which contains the code often used repeatedly in a large program.

In Subroutine is called explicity by a program stalment
100 CALL X
101
102
103 CALL X
200 SUB X
201 STATEMENT X
202
OTHER STATEMENT
300 RETURN


There are so many addressing modes such as: -
Ø Index- addressing mode.
Ø Relative- addressing mode.
Ø Indirect- addressing mode.
Ø Base- addressing mode.
Ø Direct- addressing mode.
Ø Immediate addressing mode.
Ø Displacement addressing mode
But for the above machine we can use Displacement addressing machine.

EA = A+ (R)
DA = DO (A)
EA = DA+ (R)
D = (EA)
(DA is the direct address)
IA = A + (R)
EA = (IA)
D = (EA)
(IA is Indexed address)

Short Notes: CRT Monitors, Keyboard, Inkjet printer, LAN Card, Digital Camera

(i) CRT Monitors

The cathode ray tube or CRT, invented by Karl Ferdinand Braun, is the display device that was traditionally used in most computer displays, video monitors, televisions, radar displays and oscilloscopes. The CRT developed from Philo Farnsworth's work was used in all television sets until the late 20th century and the advent of plasma screens, LCD TVs, DLP, OLED displays, and other technologies. As a result of CRT technology, television continues to be referred to as "The Tube" well into the 21st century, even when referring to non-CRT sets.

(ii) Keyboard

A hardware device consisting of a number of mechanical buttons (keys) which the user presses to input characters to a computer.

Keyboards were originally part of terminals which were separate peripheral devices that performed both input and output and communicated with the computer via a serial line. Today a keyboard is more likely to be connected more directly to the processor, allowing the processor to scan it and detect which key or keys are currently pressed. Pressing a key sends a low-level key code to the keyboard input driver routine which translates this to one or more characters or special actions.

Keyboards vary in the keys they have, most have keys to generate the ASCII character set as well as various function keys and special purpose keys, e.g. reset or volume control.

(iii) Inkjet printer

A class of printer in which small ink droplets are sprayed electrostatically from a nozzle onto the paper.

Inkjet printers are very quiet in comparison to impact printers.

A popular example is the Olivetti BJ10

(iv) LAN Card

Hardware in a computer that transmits the Ethernet, local area network (LAN) protocol over a line, wire or cable.
The ethernet card provides a standardized way of connecting computers together to create a network. Because DSL technology requirements far exceeds the lower speed limits of standard serial/parallel connections now uilt-in most PCs, a connection technology capable of interfacing at higher speeds was required; Ethernet technology, capable of sustaining traffic volumes of up to 10MB, was chosen as the technology of choice.

A network adapter that lets a computer connect to an Ethernet. The card can be a printed circuit board that is plugged into a computer or it can be built into the motherboard.

(v) Digital Camera

A camera that captures and stores still images as digital data instead of on photographic film.
The first digital cameras became available in the early 1990s[?].
A digital camera, is an electronic device used to transform images into electronic data. Modern compact digital cameras are typically multifunctional, with some devices cabable of taking photographs, video, and/or sound. 2005 saw a dramatic increase in consumer adoption of digital cameras as opposed to 35mm film cameras. North American sales of their digital counerpart exceeded, for the first time in history, sales of film cameras.

DIMM, SDRAM, FAT, Disk controllers and Archival storage devices

(i) DIMM

Dual In-line Memory Module
Small circuit boards carrying memory integrated circuits, with signal and power pins on both sides of the board, in contrast to single-in-line memory modules (SIMM).
The individual gold or lead connectors (pins) on SIMMs, although they are on both sides of the chip, are connected to the same memory chip, while on a DIMM, the connections on each side of the module connect to different chips. This allows for a wider data path, as more modules can be accessed at once. DIMM pins are arranged in a zigzag design to allow PCB tracks to pass between them.
The 8-byte DIMM format with dual-sided contacts can accommodate 4- and 16-megabit dynamic RAM chips, and is predicted to handle 64- and 256-Mbit devices. The 8-byte DIMM will hold up to 32 megabytes of memory using 16-Mbit DRAMs, but with the 256-Mbit future-generation DRAM, it will be able to hold a 64-Mx64 configuration. Another variation, the 72-pin SO-DIMM, is designed to connect directly to 32 bit data buses, and is intended for use in memory-expansion applications in notebook computers.
A Dual in-line memory module (DIMM), as opposed to SIMMs (used by the majority of the PC industry) allows for a 128-bit data path by interleaving memory on alternating memory access cycles. SIMMs on the other hand, have a 64-bit data path. Suppliers are unanimous in their belief that the DIMM will eventually replace the SIMM as the market's preferred memory module.

(ii) SDRAM

(SDRAM, Synchronous DRAM) A form of DRAM which adds a separate clock signal to the control signals. SDRAM chips can contain more complex state machines, allowing the m to support "burst" access modes that clock out a series of successive bits (similar to the nibble mode DRAM).





(iii) FAT

File Allocation Table
(FAT) The component of an MS-DOS or Windows 95 file system which describes the files, directories, and free space on a hard disk or floppy disk.
A disk is divided into partitions. Under the FAT file system each partition is divided into clusters, each of which can be one or more sectors, depending on the size of the partition. Each cluster is either allocated to a file or directory or it is free (unused). A directory lists the name, size, modification time and starting cluster of each file or subdirectory it contains.
At the start of the partition is a table (the FAT) with one entry for each cluster. Each entry gives the number of the next cluster in the same file or a special value for "not allocated" or a special value for "this is the last cluster in the chain". The first few clusters after the FAT contain the root directory.
The FAT file system was originally created for the CP/M[?] operating system where files were catalogued using 8-bit addressing. MS DOS's FAT allows only 8.3 filenames.
With the introduction of MS-DOS 4 an incompatible 16-bit FAT (FAT16) with 32-kilobyte clusters was introduced that allowed partitions of up to 2 gigabytes.
Microsoft later created FAT32 to support partitions larger than two gigabytes and pathnames greater that 256 characters. It also allows more efficient use of disk space since clusters are four kilobytes rather than 32 kilobytes. FAT32 was first available in OEM Service Release 2 of Windows 95 in 1996. It is not fully backward compatible with the 16-bit and 8-bit FATs.



(iv) Disk controllers

(Or "hard disk controller", HDC) The circuit which allows the CPU to communicate with a hard disk, floppy disk or other kind of disk drive.

The most common disk controllers in use are IDE and SCSI controllers. Most home personal computers use IDE controllers. High end PCs, workstations and network file servers mostly have SCSI adaptors.

(v) Archival storage devices

Digital information stored on magnetic tape or compact disc.

Data distribution in various levels of RAID?

How is the data distributed in various levels of RAID? Explain with the help of some example data. What should be the RAID level for the disk of database server that is used as a backend to store the critical financial information of a company? Give reasons in support of your answer.


The basic idea behind RAID is to combine multiple small, inexpensive disk drives into an array, which yield performances exceeding that of one large and expensive derive. This array of drives will appear to the computer as a single logical storage unit or drive.

RAID is a method in which information is spread across several disks, using techniques such as disk string (RAID Level 0) and disk mirroring (RAID Level 1) to achieve redundancy, lower latency and or higher bandwidth for reading and or/ writing to disks, and minimize recoverability from hard –disk crashes.

Need for RAID: -
RAID provides real-time data recovery when a hard drives fails increasing system uptime and network availability against loss of data. Another advantage of the system is that multiple disks working together increase overall system performance. Any individual or company could benefit from having a RAID recovery system in place.

Level of RAID:-

Level 0:- RAID 0, often called “striping” is a performance –oriented striped data mapping technique. That means the data being written to the array is broken dawn into strips and written across of the member disks of the array.

Level 1:- RAID Level1, or “Mirroring”, has been used longer than any other form of RAID . Level 1 provides redundancy by writing identical data to each member disk of the array leaving a “mirroring” copy on each disk. Mirroring remains popular due to its simplicity and high level of data availability.

Level 4: - Level 4 uses parity (3) concentrated on a single disk drive to protect data. It’s better suited to transaction I/O rather than file transfers. Because the dedicated parity disk represents an inherent an inherent bottleneck, level 4 is seldom used without accompanying technologies such as write-back caching.

Level 5:- The most common type of RAID. By distributing parity across some or all of an arrays member disk drives, RAID level 5 eliminates the write bottleneck inherent in level 4. The only bottleneck is the parity calculation process. With modern CPUs and software RAID, that is not a very big bottleneck.